Figure above the realization of 4 bit adder subtractor.
Design a combinational circuit for 4 bit binary subtractor.
The half subtractor is a combinational circuit which is used to perform subtraction of two bits.
Given two 4 bit positive binary numbers a and b you are to design an adder subtractor circuit to compute a b or a b depending upon a mode input which controls the operation.
A combinational logic circuit performs a subtraction between the two binary bits by considering borrow of the lower significant stage is called as the full subtractor.
The control input is controls the addition or subtraction operation.
Specifically when m 0 the circuit becomes a 4 bit adder and when m 1 the circuit becomes a 4 bit subtractor that performs the operation a plus the 2 s complement.
From the figure it can be seen that the bits of the binary numbers are given to full adder through the xor gates.
It has two inputs the minuend and subtrahend and two outputs the difference and borrow out the borrow out signal is set when the subtractor needs to borrow from the next digit in a multi digit subtraction.
However to add more than one bit of data in length a parallel adder is used.
Lets consider two 4 bit binary numbers a and b as inputs to the digital circuit for the operation with digits.
Design a 4 bit adder subtractor circuit using the 4 bit binary full adders 74ls83 and any necessary additional logic gates.
The circuit consists of 4 full adders since we are performing operation on 4 bit numbers.
The circuit has a mode input bit m that controls its operation.
A0 a1 a2 a3 for a b0 b1 b2 b3 for b.
A full adder adds two 1 bits and a carry to give an output.
A parallel adder adds corresponding bits simultaneously using full adders.
This circuit requires prerequisite knowledge of exor gate binary addition and subtraction full adder.
When the subtraction input is logic 0 the b3 b2 b1 b0 are passed to the full adders.
A parallel adder is an arithmetic combinational logic circuit that is used to add more than one bit of data simultaneously.
In this subtraction of the two digits is performed by taking into consideration whether a 1 has already borrowed by the previous adjacent lower minuend bit or not.
You may use one s or two s compliment of b to perform subtraction.